In a digital LSI (or a semiconductor integrated circuit), a data signal is taken in and synchronized with timing signals such as a clock signal and the like. Therefore, for designing a digital LSI, timing specifications are required for guaranteed operation. Major timing specifications include setup time and hold time. The setup time is a time for a data signal to be fixed and held before a timing signal arrives. The hold time is a time for a data signal to be held after a timing signal has arrived.
In general, although layout tools for digital LSIs execute layout considering such timing specifications, it is often the case that timing specification violations (timing errors) remain partially. To efficiently remove timing errors, layout needs to be corrected without influencing a part that has no timing errors. Thereupon, timing error removal has been attempted by inserting buffers and the like into a part that has timing errors, with limiting a range that is influenced by the insertion. Here, layout correction for removing timing errors is called timing ECO (Engineering Change Order).
FIG. 1 is a schematic view illustrating an example of removal of a timing error. In FIG. 1, assume that a path T1 from a sequential circuit element FF1 to another element FF4 and another path T2 from FF2 to FF4 have hold time violations (hold time errors), respectively. On the other hand, assume that a path T3 from FF3 to FF4 has no margin for setup time. Here, a path is a route in a circuit that has a data output pin of an arbitrary sequential circuit element as a start point, and a data input pin of a sequential circuit element as an end point.
In a circumstance illustrated in FIG. 1, an effective logic-level correction location may be selected along a path having a timing error, at which an insert buffer may be selected or the size of an existing cell (logic) may be reselected. The word “effective” here means that a timing error is corrected with a few inserted or replaced cells. In the example in FIG. 1, an effective solving method may be to insert a buffer B5 at a location designated with P1 (referred to as a “location P1”, hereafter) because it does not have an influence on the path T3, yet the hold time errors of the paths T1 and T2 can be removed. In this case, the buffer B5 can add a delay to data signals on the paths T1 and T2 without influencing the path T3, which removes the hold time errors on the paths T1 and T2.
Conventionally, the following steps are executed for removing such timing errors.
Step 1: Determine whether there are timing errors in a layout result.
Step 2: If there are any timing errors, select a logic-level insert location and a buffer to be inserted. For example, the location P1 and the buffer B5 are selected as illustrated in FIG. 1.
Step 3: Based on the result at Step 2, determine a physical placement position of the buffer. For example, a physical placement position of the buffer B5 is determined to be the location P1 in FIG. 1.
Step 4: Select a routing layer and a wiring pattern for a part to be wired.
Here, Step 2 and Step 3 are mutually independent. Namely, at Step 2, layout information is not referenced for selecting an insert buffer, while using a delay model that assumes no new wiring capacitances are generated when a buffer is inserted.
On the other hand, at Step 3, a netlist is received as input that reflects the logical correction generated at Step 2, to determine a physical position of an insert buffer. Here, the physical placement position of the insert buffer is limited to a vacant area where the insert buffer can be placed, hence a great error difference may be found between a delay based on the delay model at Step 2 and a delay that reflects an actual placement position.
For example, FIG. 2 is a schematic view illustrating an example of an actual placement position of an insert cell. In FIG. 2, vacant areas neighboring the location P1 (an input pin of the cell A2) in FIG. 1 is illustrated. In FIG. 2, shaded parts designate already placed instance cells. On the other hand, non-shaded white parts designate vacant areas.
If the size of the buffer B5 selected to be inserted at Step 2 is 5 (height 1, width 5), the only vacant area where the buffer B5 can be inserted is the lower-left part in FIG. 2. Therefore, the buffer B5 is placed in the lower-left vacant area at Step 3. Then, an error difference of delay arises between the signal path designated with a solid line arrow s1 in FIG. 2, on which delay calculation at Step 2 is based, and the signal path designated with dashed line arrows s2 and s3, on which delay calculation with the actual placement position is based. This point will be described in detail with reference to FIG. 3.
FIGS. 3A-3B are schematic views illustrating difference in relative distances between an insert buffer and preceding/succeeding cells before and after buffer selection.
FIG. 3A illustrates an expected position (namely, the location P1) when selecting the buffer B5. In FIG. 3A, the distance from the output pin of the cell A1 to the input pin of the buffer B5 is designated with a distance 11, and the distance from the output pin of the buffer B5 to an input pin of the cell A2 is designated with a distance 12.
On the other hand, FIG. 3B illustrates a placed position of the buffer B5 after selection. In FIG. 3B, the distance from the output pin of the cell A1 to the input pin of the buffer B5 is designated with a distance m1 (l1<m1), and the distance from the output pin of the buffer B5 to an input pin of the cell A2 is designated with a distance m2 (l2<m2).
Namely, the actual distance from the output pin of the cell A1 to the input pin of the buffer B5, and the actual distance from the output pin of the buffer B5 and the input pin of the cell A2 are longer than the expected distances obtained at Step 2.
Consequently, problems may arise, for example, the buffer B5 inserted to remove hold time errors causes a setup time error, or the hold time errors are not removed because a buffer is not inserted to avoid a setup time error. In such cases, a repeated execution of timing ECO may generate the same result, hence the location P1 selected at Step 2 in the previous execution needs to be removed from candidate correction locations, before executing timing ECO again. Such a repetition makes the whole process of timing error correction longer.
Thereupon, a method has been devised in that Steps 2 and 3 are integrated so that layout information is referenced at Step 2 (see, for example, Patent Document 1). Namely, once an insert buffer is selected, a physical placement position of the insert buffer is determined immediately. Based on the result, delay calculation and updating of slack values are executed to determine whether timing errors can be corrected. Here, a slack value is a difference between a required arrival time and an actual signal arrival time calculated assuming that setup time and hold time specifications are satisfied, which represents a delay margin.